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low power, 18 mhz variable gain amplifier data sheet AD8338 rev. 0 document feedback information furnished by a nalog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features voltage controlled gain range of 0 db to 80 db 3 ma s upply c urrent at gain of 40 db low frequency ( lf ) to 18 m hz o peration supply r ange : 3.0 v to 5. 0 v adjustable g ain r ange low n oise : 4.5 nv/ hz fully d ifferential s ignal p ath o ffset correction (o ffset null) feature adjustable b andwidth in ternal 1.5 v r eference 16- lead lfcsp automatic g ain c ontrol f eature wide gain range for high dynamic range signals applications front e nd for in ductive t elemetry s ystems ultrasonic s ignal r eceivers rf b aseband s ig nal c onditioning general description the AD8338 is a variable gain amplifier (vga) for applications that require a fully differential signal path, low power, low noise , and a well - defined gain over frequencies from lf to 18 m hz. the device can also operate using single - ended sources if required. the basic gain function is linear - in - db with a nominal gain range of 0 db to 80 db; the nominal gain range corresponds to a control voltage on the gain pin of 0.1 v to 1.1 v. the gain range can be adjusted up or down via direct access to the internal summing nodes at the inpd and inmd pins. for example, if a 47 ? resistor is applied to the inpd and inmd pins, a gain range of 20 db to 100 db is set with an inp ut referred noise level of 1.5 nvhz. the AD8338 includes additional circuits to enable offset correction and automatic gain control (agc). dc offset voltages are removed by the offset correction c ircuit, which behaves like a high - pass filter. the high - pass filter corner frequency is set using an external capacitor. the agc function varies the gain of the AD8338 to maintain a constant rms ou tput voltage. a user supplied voltage controls the ta rget output rms voltage. a user supplied capacitor to ground at the deto pin controls the response time of the agc circuit. functional block dia gram inpr inpd inmd inmr mode comm gain fbkm outp outm deto vagc fbkp + ? + ? vref vga core 0db to 80db offset null output stage 0db ofsn vref vbat automatic gain control gain interface AD8338 11279-001 figure 1 . 100 ?40 ?20 0 20 40 60 80 10k 100m 10m 1m 100k gain (db) frequency (hz) v gain = 0.1v v gain = 0.2v v gain = 0.3v v gain = 0.4v v gain = 0.5v v gain = 0.6v v gain = 0.7v v gain = 0.8v v gain = 0.9v v gain = 1.0v v gain = 1.1v 1 1279-005 figure 2 . gain vs. frequency the AD8338 offers additional versatility by allowing user access to the internal summing nodes. with a few discrete components, users can customize the gain, bandwidth, input impedance, and noise profile of the part to fit their application. the AD8338 uses a single supply voltage of 3.0 v to 5. 0 v and is very power efficient, consuming as little as 3 ma quiescent current. the AD8338 is available in a 3 mm 3 mm, rohs compliant, 16- lead lfcsp. it is specified over the industrial temperature range of ? 40c to + 8 5c .
AD8338 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac specifications .......................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteri stics ............................................. 6 theory of operation ...................................................................... 12 getting started with the AD8338 ............................................. 12 offset correction circuit .......................................................... 12 explanation of the gain function ............................................ 12 agc circuit ................................................................................ 13 adjusting the output common - mo de volt age ..................... 14 applications information .............................................................. 15 simple on - off keyed (ook) receiver ................................... 15 interfacing the AD8338 to an adc ......................................... 15 outline dimensions ....................................................................... 16 orderi ng guide .......................................................................... 16 revision history 4/1 3 revision 0: initial version
data sheet AD8338 rev. 0 | page 3 of 16 specifications ac specifications vbat = 3.0 v, t a = 25c, c l = 2 pf on outp and outm, r l = , mode pin high, r in = 2 500 , v gain = 0.6 v, differential operation, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit input interface gain range standard configuration using the inpr and inmr inputs 0 80 db gain span 80 db input voltage range 3 v p-p input 1 db compression differential input, v cm = 1.5 v, gain = 0.1 v/0 db f = 400 khz 2.2 v p-p f = 1 mhz 2 v p-p f = 4 mhz 1.6 v p-p f = 10 mhz 0.75 v p-p ?3 db bandwidth 18 mhz gain accuracy standard configuration using the inpr and inmr inputs; 0.1 v < v gain < 1.1 v ?2 +0.5 +2 db input resistance standard configuration using the inpr and inmr inputs 0.8 1 1.2 k input capacitance 2 pf output interface outp and outm pins small signal bandwidth v gain = 0.6 v 18 mhz peak slew rate v gain = 0.6 v 50 v/s peak-to-peak output swing diff erential output 2.8 v p-p common-mode voltage 1.5 v input-referred noise voltage standard configuration using the inpr and inmr inputs 4.5 nv/hz driving external 47 input resistors connected to inpd and inmd 1.5 nv/hz offset voltage rto, v gain = 0.1 v, offset null on ?10 +10 mv rto, v gain = 0.6 v, offset null on ?10 +10 mv rto, v gain = 0.1 v, offset null off ?50 +50 mv rto, v gain = 0.6 v, offset null off ?200 +200 mv power supply vbat 3.0 5.0 v i vbat min gain, v gain = 0.1 v 6.0 8.0 ma mid gain, v gain = 0.6 v 3.0 3.8 ma max gain, v gain = 1.1 v 4.5 6.0 ma gain control gain voltage 0.1 1.1 v gain slope 77 80 83 db/v 12.5 mv/db vref accuracy vref = 1.5 v 2 % deto output current 10 a agc control mode = 0 v maximum target amplitude expected rms output value for target = vagc ? vref = 1.0 v 1.0 v rms
AD8338 data sheet rev. 0 | page 4 of 16 absolute maximum rat ings tab le 2. parameter rating vbat to comm ?0.3 v to +5. 5 v inpr, inpd, inmd, inmr, mode , gain, fbkm, fbkp, outm, outp, vagc, vref , ofsn comm to vbat operating temperature range ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 3 . thermal resistance package type ja unit 16- lead lfcsp 48.75 c/w esd caution
data sheet AD8338 rev. 0 | page 5 of 16 pin configuration and function descrip tions 1 inpr 2 inpd 3 inmd 4 inmr 11 outp 12 fbkp 10 outm 9 fbkm 5 comm 6 mode 7 gain 8 deto 15 vbat 16 vref 14 ofsn 13 vagc AD8338 top view (not to scale) notes 1. the exposed pad should be tied to a quiet analog ground. 1 1279-002 figure 3 . pin configuration table 4 . pin function descriptions p in no. mnemonic description 0 epad exposed pad . the exposed pad should be tied to a quiet analog ground . 1 inpr positive 500 ? r esistor i nput for voltage input a pplications . 2 inpd positive input for current input applications . 3 inmd negative input fo r current input applications . 4 inmr negative 500 ? r esistor i nput for voltage input a pplications . 5 comm ground . 6 mode gain mo de. this pin s elects positive or negative gain slope for g ain control . when this pin is tied to vbat, the gain of the AD8338 increases proportionally with an increase of the voltage on the gain pin. when this pin is tied to comm, the gain decreases with an increase of the voltage on the gain pin. 7 gain gain c ontrol inp ut, 12.5 mv/ db or 80 db/v . 8 deto detector output t erminal, 10 a . if the agc feature is not used , tie t his pin t o comm . 9 fbkm negative feedback node . for more information, see the adjusting the output common -mo de voltage section. 10 outm negative output . 11 outp positive output . 12 fbkp positive feedback node . for more information, see the adjusting the output common - mode voltage section. 13 vagc voltage for automatic gain control circuit. this pin c ontrols the target rms output voltage for the agc c ircuit . for more information, see the agc circuit section. 14 ofsn offset n ull t erminal . for more information, see the offset correcti on circuit section. 15 vbat positive supply voltage . 16 vref i nternal 1.5 v voltage reference .
AD8338 data sheet rev. 0 | page 6 of 16 typical performance characteristics 80 0 10 20 30 40 50 60 70 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 gain (db) v gain (v) mode pin low mode pin high 1 1279-003 figure 4 . gain vs. v gain 80 0 10 20 30 40 50 60 70 number of hits gain slope (db/v) 78.0 78.3 78.6 78.9 79.2 79.5 79.8 80.1 80.4 11279-105 figure 5 . gain slope histogram 100 ?40 ?20 0 20 40 60 80 10k 100m 10m 1m 100k gain (db) frequency (hz) v gain = 0.1v v gain = 0.2v v gain = 0.3v v gain = 0.4v v gain = 0.5v v gain = 0.6v v gain = 0.7v v gain = 0.8v v gain = 0.9v v gain = 1.0v v gain = 1.1v 1 1279-106 f igure 6 . gain vs. frequency 80 ?60 ?40 ?20 0 20 40 60 100k 1m 10m 100m gain (db) frequency (hz) v gain = 100mv v gain = 350mv v gain = 600mv 1 1279-109 figure 7 . gain vs. frequency , r in = 50 ? 80 ?80 ?60 ?40 ?20 0 20 40 60 100k 1m 10m 100m gain (db) frequency (hz) v gain = 100mv v gain = 350mv v gain = 600mv v gain = 850mv v gain = 1100mv 1 1279-107 figure 8 . gain vs. frequency, r in = 5 k? 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 gain error (db) v gain (v) ?40c +25c +85c +105c v s = 3v f = 1mhz 1 1279-006 figure 9 . gain error vs. v gain over t emperature
data sheet AD8338 rev. 0 | page 7 of 16 1.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 gain error (db) v gain (v) 10khz 100khz 1mhz 2mhz 4mhz 8mhz 10mhz 12mhz 14mhz 1 1279-007 figure 10 . gain error vs. v gain over frequenc y 30 0 5 10 15 20 25 100k 1m 10m 100m delay (ns) frequency (hz) 1 1279- 1 10 figure 11 . group delay vs. frequency 0 10 20 30 40 50 60 number of hits differential offset voltage (mv) ?3 ?2 ?1 0 1 2 1 1279- 11 1 offset null on relative to output v gain = 0.6v figure 12 . differential offset voltage histogram 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 offset voltage (mv) referred to output v gain (v) ?40c +25c +85c +105c v s = 3v 1 1279-012 figure 13 . differential offset voltage vs. v gain , offset null on 350 300 0 50 100 150 200 250 100k 1m 10m 100m impedance () frequency (hz) single-ended differential 1 1279- 1 12 figure 14 . outp ut impedance vs. frequency 20 ?120 ?100 ?80 ?60 ?40 ?20 0 100k 1m 10m 100m balance error (db) frequency (hz) 11279-015 gain = 1 gain = 10 gain = 100 gain = 1000 figure 15 . output balance error vs. frequency
AD8338 data sheet rev. 0 | page 8 of 16 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10k 100k 1m 10m cmrr (db) frequency (hz) 0db 20db 40db 60db 80db 1 1279- 1 15 figure 16 . cmrr vs. frequency over gain, offset null on, referred to input 100k 10k 1k 100 0 0.4 0.8 1.2 0.3 0.7 1.1 0.2 0.6 1.0 0.1 0.5 0.9 noise (nv/ hz) v gain (v) 11279-017 ?40c +25c +85c figure 17 . output re ferred noise vs. v gain 1k 1 10 100 0 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 noise (nv/ hz) v gain (v) ?40c +25c +85c 11279-119 figure 18 . input referred noise vs. v gain 1000 0.1 1 10 100 10k 100k 1m 100m 10m noise (nv/ hz) frequency (hz) gain = 1, offset null off gain = 10, offset null off gain = 100, offset null off gain = 1000, offset null on gain = 10000, offset null on 1 1279- 1 17 figure 19 . input referred noise vs. frequency , vbat = 3 v 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 50k 500k 5m harmonic distortion (dbc) frequency (hz) hd2, 1k hd3, 1k hd2, 10k hd3, 10k v out = 0.5v p-p 11279-118 figure 20 . harmonic distortion vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 0.5 3.0 2.5 2.0 1.5 1.0 harmonic distortion (dbc) v out (v p-p) hd2 hd3 11279-120 figure 21 . harmonic distortion vs. output amplitude
data sheet AD8338 rev. 0 | page 9 of 16 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 0.1 1.1 0.9 0.7 0.5 0.3 1.0 0.8 0.6 0.4 0.2 harmonic distortion (dbc) v gain (v) hd2, mode pin high hd3, mode pin high hd2, mode pin low hd3, mode pin low 11279-123 v out = 0.5v p-p figure 22 . harmonic distortion vs. v gain 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 0.1 0.3 0.5 0.7 0.9 1.1 p1db compression (dbm) v gain (v) 11279-122 output input figure 23 . input and output 1 db compression vs. v gain 25 0 5 10 15 20 0.1 1.1 0.9 0.5 0.7 0.3 oip3 (dbm) v gain (v) 11279-125 100khz 1mhz figure 24 . oip3 vs. v gain 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 20k 20m 2m 200k imd3 distortion (dbc) frequency (hz) 11279-124 figure 25 . imd3 distortion vs. frequency 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 100 200 300 400 500 600 700 800 v out (v) time (ns) v out = 2v p-p f = 1mhz gain = 0db 1 1279-027 figure 26 . large signal pulse respons e vs. time, v gain = 0 v 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 v out (v) time (s) v out = 2v p-p f = 1mhz gain = 80db 1 1279-028 figure 27 . large signal pulse resp onse vs. time, v gain = 1.0 v
AD8338 data sheet rev. 0 | page 10 of 16 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 v out (v) time (s) v out = 2v p-p f = 1mhz gain = 40db 1 1279-030 figure 28 . large signal pulse response vs. time, v gain = 0. 6 v 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 0 0.2 0.4 0.6 0.8 v out (mv) time (s) c l = 0pf c l = 10pf c l = 20pf c l = 47pf v out = 100mv p-p f = 1.5mhz gain = 1 1 1279-031 figure 29 . small signal pulse response vs. time (varying capacitive loads) 0.6 0.1 1.0 0 ?1.0 0 10 8 6 4 2 9 7 5 3 1 gain step (v) time (s) 11279-127 v gain v out figure 30 . gain step response vs. time 1.5 0.5 1.0 0 ?0.5 ?1.5 ?1.0 0 80 160 200 60 140 40 120 20 100 180 output voltage (v) time (s) 11279-018 f = 100khz v in low = 2mv v in high = 20mv gain = 40db figure 31 . overdrive recovery vs. time 12 10 8 6 4 2 0 0 1.2 1.1 1.0 0.8 0.6 0.4 0.2 0.9 0.7 0.5 0.3 0.1 i dd (ma) v gain (v) ?40c, mode pin high +25c, mode pin high +85c, mode pin high ?40c, mode pin low +25c, mode pin low +85c, mode pin low 1 1279-131 figure 32 . supply current vs. v gain 50 ?40 ?30 ?20 ?10 0 10 20 30 40 20 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) 11279-134 0.01f 0.1f 1f 10f offset null off gain = 100 figure 33 . offset null bandwidth vs. offset null capacito r
data sheet AD8338 rev. 0 | page 11 of 16 0 ?10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 1 1279-133 figure 34 . psrr vs. frequency 0.6 0.1 0 ?1.0 1.0 0 10 30 40 5 25 20 15 35 voltage (v) time (s) 11279-019 agc voltage output voltage figure 35 . agc response vs. time , no load 0.6 0.1 0 ?1.0 1.0 0 2 6 10 9 8 1 5 4 3 7 voltage (v) time (ms) 11279-020 agc voltage output voltage figure 36 . agc response vs. time , c l = 0.01 f 3.0 0 0.5 1.0 1.5 2.0 2.5 20k 100k output common-mode voltage (v) resistance () v s = 3v v s = 5v 11279-135 figure 37 . output c ommon - mode voltage vs. r cm to vbat 3.0 0 0.5 1.0 1.5 2.0 2.5 10k 100k output common-mode voltage (v) resistance () v s = 3v 11279-136 figure 38 . output common - mode voltage vs. r cm to comm
AD8338 data sheet rev. 0 | page 12 of 16 theory of operation getting s tarted with the AD8338 the AD8338 is a variable gain amplifier (vga) that provides a variable gai n range of 80 db . with a constant ? 3 db bandwidth of 18 mhz across all gains, a gai n bandwidth product of 18 0 ghz is achieved at the highest gain using only 4.5 ma of supply current . the differential output allows the AD8338 to dir ectly drive an adc input, simplifying board design and saving space and power. in addition to its gain, bandwidth , and power performance, the AD8338 includes a range of features that increase its v ersatility . ? single - supply operation ranging from 3.0 v to 5. 0 v ? b uilt - in offset correction circuit to cancel out dc offsets ? automatic gain control (agc) circuit to control the gain and keep the output at a steady rms level access to internal nodes at both the input and output allow s the user to adjust the gain ran ge, adjust the output common - mode voltage , and tun e the bandwidth. inpr and inmr pins in the standard configuration the gain is controlled by a user suppli ed voltage input applied to the gain pin . t he gain can be varied from 0 db to 80 db when the default internal resistors are used ; the voltage at the gain pin can be varied from 0.1 v to 1.1 v . the default internal resistors are used by applying the input voltage to the inpr and inmr pins ( p in 1 an d pin 4 ; see figure 39). inpr inpd inmd inmr ? ? i in v in 0db to 80db outp outm +v out /2 + vref ?v out /2 + vref 1 1279-043 figure 39 . input voltage applied to the inpr and inmr pins in the standard configuration, a differential input voltage applied across inpr and inmr is amplified, with the output voltage appearing differentially across outp and outm . th e outputs have a default common - mode voltage of vref , which is eq ual to 1.5 v . gain and mode pins the gain of the AD8338 is controlled by the gain and mode pins . adjusting the voltage at th e gain pin from 0.1 v to 1.1 v adjust s the gain from its lowest to highest value . the mode pin controls the polarity of the gain adjustment . when mode is tied to vbat, the gain of the AD8338 increases propor - tionally with an increase of the voltage on the gain pin . when mode is tied to comm , the gain decreases with an increas e of the voltage on the gain pin. offset correction ci rcuit the AD8338 provides an offset correction circuit to cancel out any dc offsets that may be present. connecting a 0.2 f capacitor from the ofsn pin to vref allows frequencies above 400 hz to pass th rough, but eliminate s dc offsets. for dc - coupled operation, disable the offset correction circuit by connecting the ofsn pin directly to the comm pin . when the part is operated with out o ffset correction , exercise caution with large gains because any offset s present large errors on the outputs. unlike a high - pass filter, the offset correction circuit allows signals below the corner frequency to pass through with high levels of crossover distortion. if a frequency below the band of interest may present itself to the inputs, apply a filter in front of the vga for best performance. for lower frequency operation, a larger value of c ofsn gives unpredictable results. if the part is operated at frequencies b elow 400 hz, disable the offset correction circuit and comp ensate the offset externally. the corner frequency can be approximately calculated as follows : ofsn c c f = 600 2 1 (1) explanation of the gain function f rom a designers standpoint, the gain of the AD8338 can be modeled as three cascaded gain stages. the first stage can be thought of as a differential in put transconductance stage, where the in put current is proportional to the differential input voltage that is applied to the input resistors , as follows : n p in r r inmx inpx i + ? = (2) this current is then fed into the conceptual second stage, a current in put - current out put vga, which has a gain range of ?26 db to +54 db. the conceptual output current is given by equation 3. i out_vga = i in 10 ?26 + 80 (( v gain ? 0. 1) /20 ) (3) when v gain = 0.1 v, the output current is ?26 db less than the input current ; when v gain = 1.1 v, t h e output current is +54 db greater than the input current. the third and final stage can be modeled as a trans impedance stage, expressed as follows : v op = i out_vga r feedback (4a) v o n = ? i out_vga r feedback (4b) v out = v op ? v o n = 2 i out_vga r feedback (4c)
data sheet AD8338 rev. 0 | page 13 of 16 for example, if the 500 input resistors and 9.5 k feedback resistors are used and a 1 v p - p signal is applied wit h v gain set to 0.1 v, the output value is as follows : i in = 1 /(500 + 500) = 1 ma (5a) i out_vga = 1 ma 10 ?26/20 = 50 a (5b) v out = 2 50 a 9.5 k? = 0.95 v p - p (5c) the calculation in equation 5 results in a total gain of a pprox - imately ? 0.4 db under the specifi ed conditions. compressing e quation 2 through equation 4 produces the following simplified gain equation: gain (d b ) = ( v gain ? 0.1) 80 + 20log( r feedback / r in ) ? 26 (6) where r feedback and r in are the resistor values from a single input to a sin gle output. 11279-200 inpr inpd inmd inmr mode comm gain deto vagc vga core ?26db to +54db offset null ofsn vref vbat automatic gain control gain interface AD8338 9.5k? 9.5k? vref fbkp outp outm fbkm i out i in 500? 500? figure 40 . functional block diagram for example, if a desig n require s a minimum gain of 20 db using a few additional components, e quation 6 shows that applying a 47 resistor to both the inpd and inmd pins (overridin g the value of r in ) sets a gain range of 2 0 db to 100 db (see figure 41 ) . inpr inpd inmd inmr 500? 500? 47? 47? i in v in 20db to 100db outp outm +v out /2 + vref ?v out /2 + vref 1 1279-044 figure 41 . using external resistors at the inpd and inmd pins similarly, if the user requires a minimum gain of ?10 db, applying a 1.5 k? resistor to both the inpd and inmd pins sets a gain range of ?10 db to +70 db. effects o f using external resistors when the gain is modified through the use of external resistors, several trade - o ffs must be considered . for exam ple, w ith the appli - cation of 47 ? resistors at the inputs, th e input noise decreases to approximately 1.5 nv/hz, less than the 4.5 nv/hz obtai ned when using the internal 500 ? resistors. however, the ?3 db bandwidth is reduced from 18 m hz to approximate ly 3 mhz . agc circuit the automatic gain control (agc) circuit compares the rms output of the part with the desir ed rms output at the vagc pin. based on this comparison, the deto pin either source s or sink s current. by connecting the deto and gain pins tog ether and by connecting the mode pin to ground, the agc circuit can be used to keep the output rms voltage con s tant. t o ensure that the agc circuit reacts fast enough to adjust the gain, but slow enough to allow signals through, place a capacitor from deto to ground . for example, in a n on - off keying ( ook ) application wi th a carrier frequency of 6.795 mh z and a bit rate of 10 kb/s ec , a capacitor value of 0.01 f is recommended . this value ensure s that th e gain react s to the bit en ergy but does not react to t he carrier signal. to s et the target rms output voltage , apply a voltage to vag c . the target output voltage is lowest when vag c is set to 1.5 v and increases when the applie d voltage d iverge s from the 1.5 v reference voltage. to enable an increasing voltag e at the vagc pin to increase the rms output voltage , use e quation 7. v orms = 1.7 vagc ? 2.264 (7) to enable a decreasing voltage at the vagc pin to increase the rms output voltage, use equation 8. v orms = ? 1.7 vagc + 2.864 (8) if the agc feature is n ot used, t ie th e det o pin to comm .
AD8338 data sheet rev. 0 | page 14 of 16 adjusting the output common - mode voltage as with any differential output, the output of the AD8338 is a differential voltage that is centered about a common - mode voltage . the output common - mode voltage (v ocm ) of the AD8338 is nominally set to 1.5 v using an internal reference (see figure 42) . 9.5k? 9.5k? vref = 1.5v fbkp outp = 1.5v + v out /2 outm = 1.5v ? v out /2 fbkm i out 1 1279-045 figure 42 . output common - mode voltage set to 1.5 v (default setting) the output common - mode voltage of the AD8338 can be adjusted to directly drive adcs with various input common - mode requirements . to a djust the output common - mode voltage , add a resistor from each feedback node (fbkp and fbkm) to either comm or vbat . adding a resistor from each feedback node to vbat decrease s the output common - mode voltage ; add - ing a resistor from each feedback node to comm increases the output common - mode voltage (see figure 43 and figure 44) . table 5 and table 6 provide examples of resistor values for decreasing or increasing the output common - mode voltage. table 5 . resistor v alues for d ecreasing the output common - mode voltage (resistor tied to vbat) vbat (v) target v ocm (v) re sistor value (?) tied to 5.0 0.9 55,417 vbat 3.3 0.9 28,500 vbat 3.0 0.9 23,750 vbat table 6 . resistor values for increasing the output common - mode voltage (resistor tied to comm) vbat (v) target v ocm (v) r esistor value (?) tie d to any 1.8 47,500 comm any 2.0 28,500 comm any 2.5 14,250 comm 9.5k? r1 r2 9.5k? vref = 1.5v fbkp fbkm vbat vbat i out outp = 1.5v ? + v out /2 (vbat ? 1.5v) 9.5k ? r1 outm = 1.5v ? + v out /2 (vbat ? 1.5v) 9.5k ? r2 1 1279-046 figure 43 . decreasing the output common - mode voltage (resistors connected between the fbkp and fbkm pins to the vbat pin) 9.5k? r1 r2 9.5k? vref = 1.5v fbkp fbkm comm comm i out outp = 1.5v ? + v out /2 (0 ? 1.5v) 9.5k ? r1 outm = 1.5v ? + v out /2 (0 ? 1.5v) 9.5k ? r2 1 1279-047 figure 44 . in creasing the output common - mode voltage (resistors connected between the fbkp and fbkm pins to the comm pin) the AD8338 uses its internal reference for all signal processing. therefore, a lthough the output common - mode voltage can be changed through the application of external resistors, the vref signal cannot be changed. for applications that require dc coupling to an adc, a differential amplifier must be used.
data sheet AD8338 rev. 0 | page 15 of 16 applications informa tion the excellent performance of the AD8338 results in a flat response over various gains with rail - to - rail output signa l swing, high drive capability, and a very high dynamic range at a low 12 mw . th e se features make the AD8338 an exceptional choice for use in battery - operated eq uipment, low frequency and base band applic ations, and many other applications . s imple o n - o ff keyed (ook) r eceiver for low complexity, low power data communications, a simple link built using a modulating carrier tone in an on / off s tate provides a fast and cost - effective solution to the designer. such designs are use d in a variety of applications, including near - field com munications among noninter ference mechanical systems, low data ra te sensors, rfid tags , and so on . the schematic shown in figure 45 demonstrates a complete i nductive telemetry o n - o ff k eyed ( ook) front end. the c rystal is cut for t he target receive frequency of interest, creating a very narrow - band filter, typically around the 6.78 mhz ism band. the AD8338 amplifies the signal (the gain is set by an external controller ) and drives a full - wave rectifier bridge. the output of this bridge is then low - pass filtered into 100 ? terminations. this design provides exce llent rejection of rf and excellent baseband information recovery for t he decision stage that follows. the reactive filter com ponents capacitors c1 through c4 and i nductors l1 and l2 set the baseband recovery performance. a design trade - off exchanges baseband response for rf attenua tion. table 7 provides typical values for these components at two data rates. note that c apacitors c1 through c4 are all of equal value, and i nductor l2 has the same value as l1. table 7 . typical v alues for c omponents in r eactive f ilter data rate c1 to c4 l1 and l2 carrier atten uation, f = 6.78 mhz 19,200 bps 12 nf 240 h ?101 db 57,600 bps 3.9 nf 82 h ?73 db interfacing the AD8338 to an adc the AD8338 is w ell suited to drive a high speed analog - to - digital converter (adc) and is compatible with many adcs from analog devices, inc . this example illustrates the interfacing of the AD8338 to the ad7451 . the ad7451 is a low power, 3.0 v adc, which is also competitively priced for a low cost total solution. figure 46 shows the basic connections between the AD8338 and the ad7451 . the common - mode voltage provided by the AD8338 is within the specifications of the ad7451 . the AD8338 can be coupled directly to the ad7451 for full dc - to - 18 mhz operation at the highest level of performance with low operating power (160 mw typical). the glueless interface enables a physically small, high performance data acquisit ion system that is ideal for many field instruments. a filter before the vga provides the antialiasing function and noise limiting. in applications where the modulated information is not encoded in the signal amplitude, use the agc feature of the AD8338 to reduce any bit errors in the sampled signal. vref mode vref outp outm comm ofsn crystal antenna c tune u1 AD8338 c6 0.01f gain 3.0v inpr inmr deto c5 0.1f d1 d2 d4 d3 c1 c3 c2 c4 l1 l2 r1 100? r2 100? ook_p ook_m 1 1279-048 figure 45 . c omplete, l ow power ook receiver vref mode vref outp outm comm ofsn u1 AD8338 filter output 3.0v 3.0v inpr inmr deto c3 0.1f sclk gnd ad7451 v in+ v in? c1 0.1f c2 0.1f sdata cs v dd v ref r1 49.9? to micro- controller 11279-049 figure 46 . basic c onnections to the ad7451 adc
AD8338 data sheet rev. 0 | page 16 of 16 outline dimensions 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 se a ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 47 . 16- lead lead frame chip scale package [lfcsp_ w q] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters ordering g uide model 1 temperature range package description package option branding AD8338acpz -r7 ?40c to + 8 5c 16- lead lead frame chip scale package [lfcsp_ w q] cp -16-22 y4k AD8338acpz - rl ?40c to + 8 5c 16 - lead lead frame chip scale package [lfcsp_ w q] cp - 16 - 22 y4 k 1 z = rohs compliant part. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11279 - 0- 4/13(0)

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